SysTick is an ARM register. Since the GD32VF103 doesn’t have an ARM core, it doesn’t have SysTick. Yes, I know that the User Manual references SysTick (v1.2, p63):
The RISCV System Timer (SysTick) external clock is clocked with the AHB clock (HCLK) divided by 4.
However, if you look at the GD32F103 User Manual, which the GD32VF103 User Manual was clearly based on, you see this (v2.2, p83):
The Cortex System Timer (SysTick) external clock is clocked with the AHB clock (HCLK) divided by 8.
GigaDevice probably just did a find-and-replace of “Cortex” for “RISCV” and forgot to update the rest of the passage. That’s not the only such mistake in the User Manual: earlier in that section, it says you can trigger a reset using the “RISC-V Application Interrupt and Reset Control Register.” That register doesn’t exist on RISC-V, but it does on ARM.
That being said, all hope is not lost. While RISC-V doesn’t have SysTick, it does have
mtime which serves much the same purpose. I’m almost certain that GigaDevice hooked up the clock line labeled SysTick to
mtime and just forgot to update the name in the User Manual. You can find full documentation of
mtime in the RISC-V Privileged ISA Specification and also in the Bumblebee Core Architecture Manual.
Interestingly, neither the GD32VF103 User Manual nor the Bumblebee Architecture Manual say where
mtime is mapped into memory. The latter at least makes some reference to it, but all it says (p62) is to “refer to the Datasheet of the Bumblebee Core.” The Bumblebee Datasheet just says (p9) to “refer to the datasheet of the specific MCU chip.” Going off @loboris’s comment above, I’d guess that the base address for the timer registers is
0xD1000000 on the GD32VF103.