SPI and the fm.fpioa pin list

I recently started porting some SPI example code from Arduino over to MaixPy. While reading through google-translated versions of the SPI docs I found the following information for the machine.SPI class:

  • mosi : MOSI (master output) pin, which can directly transmit the pin value, the value range is [0,47]. Instead of setting it up, use fm to manage pin mappings.
  • miso : MISO (master input) pin, which can directly transmit the pin value, the value range is: [0,47]. Instead of setting it up, use fm to manage pin mappings.

I’ve looked through the fpioa code, including the code from the SDK, and cannot find any reference to SPI0_MOSI, SPI0_MISO, SPI1_MOSI, or SPI1_MISO. All of the examples I can find just use miso= and mosi= for the pin instead of using fm like the documentation mentions. I can’t find any examples of using fm for mapping the SPI data pins like this. Does anyone know what the correct fpioa pin mappings are for MISO/MOSI, or should I just ignore the documentation and follow the examples?

The SPI peripherals of the k210 are kinda special. I think they are not really standard (e.g. they have parallel IO specially designed for LCD output). Maybe the example in the standalone SDK demo can help you. They seem to use two pins of the parallel SPI, one for MISO and one for MOSI. But I haven’t studied this thoroughly.

Thanks for that link. It looks like this is the important bit to grab from it. D0 is MOSI, D1 is MISO. I’ll try that out on this end and see if it works.

fpioa_set_function(SPI_MASTER_MISO_PIN, FUNC_SPI0_D1);
fpioa_set_function(SPI_MASTER_MOSI_PIN, FUNC_SPI0_D0);

It seems to be a quite old thread… but I have problem with the SPI.
As per the available documentation and digging the source, I think SPI1 can be used for SPI communication in MASTER mode having no impact on the TF card. Although it is not clear how to do this…

Practical difficulties to implement SPI communication with nrf24L01
As per the Maixduino board specification, more SPI interfaces are available, although one of them is used for the TF card management. Therefore SPI1 is mapped to generic IO port, but no clear instruction how to address and read/write specific registers. Even I am not sure if the “csn” control works properly in below snippet.

kép

import ustruct as struct
import utime
from machine import SPI
from Maix import GPIO
from Maix import FPIOA
from board import board_info
from fpioa_manager import fm

### Set up the SPI ports
fm.register(11,fm.fpioa.GPIOHS11, force=True)#cs0=csn
csn = GPIO(GPIO.GPIOHS11, GPIO.OUT)

fm.register(14,fm.fpioa.GPIOHS8, force=True)#ce
ce = GPIO(GPIO.GPIOHS8, GPIO.OUT)

fm.register(10,fm.fpioa.SPI1_D0, force=True)#mosi
fm.register(12,fm.fpioa.SPI1_D1, force=True)#miso
fm.register(13,fm.fpioa.SPI1_SCLK, force=True)#sclk

### init SPI1
spi1 = SPI(SPI.SPI1, mode=SPI.MODE_MASTER, baudrate=4000000, polarity=0, phase=0, bits=8, firstbit=SPI.MSB)

b= bytearray(1)
print("\nbefore init: ", b[0])

### init
csn.value(1)
ce.value(0)

utime.sleep_ms(500)

### prepare for communication
csn.value(0)

print("csn: ", csn.value())

spi1.write(0x03, cs=SPI.CS1)
#spi1.write(0x03)
csn.value(1)
utime.sleep_ms(500)
print("csn: ", csn.value())

csn.value(0)

# spi1.readinto(b, write=0x00, cs=SPI.CS1)
b = spi1.read(8)
csn.value(1)

ret = b[0]

print("after init: ", ret)

Expected behavior
It is planned to send 0x03 command to register 0x00 Configuration register.
But unfortunatelly, it is not clear how to address registers with the given SPI library.

Actual behaviour
As it seems, even the “csn” state change does not work.

before init:  0
csn:  0
csn:  0
after init:  0
  • IDE version: MaixPy 0.2.4
  • Firmware version: MicroPython v0.5.0-200-g8f6aa7b on 2020-08-31; Sipeed_M1 with kendryte-k210
  • Board: Maixduino
  • OS: Windows

The SPI peripherals of the k210 are kinda special.

For reference, SPI0-2 are Designware APB SSI, and SPI3 is DesignWare Cores SSI.

I think they are not really standard (e.g. they have parallel IO specially designed for LCD output)

This is standard. Think of it like octal-spi instead of e.g. dual or quad spi.

They seem to use two pins of the parallel SPI, one for MISO and one for MOSI. But I haven’t studied this thoroughly.

Yes. Off the top of my head, I believe if you use just “regular” SPI, then you use D0 as MOSI and D1 as MISO.